1. Technical Field of the Invention
This invention relates to a method and apparatus of making and using a reusable test socket or probe card for testing and contacting unpackaged semiconductor devices, semiconductor wafers, bare and populated printed circuit boards, and other fine pitch devices such as chip-scale packages and ball-grid array packages.
2. Description of Related Art
Multi-chip Modules (MCMs), or Hybrid Integrated Circuits, are manufactured by combining multiple integrated circuit dies within one package. Yield rates for such MCMs are usually low because if any one of the die within a MCM malfunctions, the entire package is considered defective. For example, MCMs which contain 20 individual die, with an average yield rate of 97.3%, would be expected to have an overall yield rate of 57.3% because of the cumulative effect of the individual yield rates of each die. Because the sum cost of the die can be quite expensive, the production of MCMs is frequently unprofitable and the cost to the consumer of MCMs is frequently unjustifiable.
Thus, there is a need to certify that each individual die is a "known good die" prior to packaging the die within the MCM. Some prior art references describe attempts to produce a known good die by first packaging the die, conducting tests at various temperatures, subjecting the integrated circuit to "burn-in" at elevated temperature, recovering the die by destroying the packaging to remove the die and then placing it within the hybrid circuit or MCM. Such a process is labor intensive and expensive and still could result in uncertainty in determining whether a die is a "known good die." Thus, there is a need for a device and method for testing bare die which allow bare die to be tested in a more cost effective manner.
Other prior art references disclose various probe cards which test the die while on the wafer. Some prior art references, such as U.S. Pat. No. 5,103,557 issued to Leedy, disclose performing tests before the metallization layers are added to the individual die still contained on the semiconductor wafer. These tests, however, only certify that a die is good at this stage in its manufacturing cycle. The completely manufactured die is not tested. It is important to test the completely manufactured die because defects can be introduced, not only when the metallization layers are added, but also when the die is separated from the semiconductor wafer.
A problem with the above device and test methods is the utilization of rigid metal probes or probes with rigid metal tips for establishing electrical continuity. Such probes are difficult to manufacture and require high maintenance. Because the individual probes are so minute, the practical difficulties of using probe cards include keeping the probes straight, keeping them at an even or planar height, and establishing electrical contact through all of the probes in the proper location simultaneously without exerting so much pressure on the semiconductor wafer that it is damaged. Additionally, the mere act of establishing electrical contact with the proper points within a circuit can be a challenging task. Frequently, special lenses or cameras are required to accomplish this task. Thus, there is a need for a device which allows the task of connecting test equipment to the die to be routine, simple and quick.
Another problem with using probe cards as disclosed by Leedy is that they typically have inherent frequency response characteristics which inhibit full functional testing of an integrated circuit throughout the desired frequency ranges. Further, these types of probe cards are designed to contact a die while it is still an integral part of the entire semiconductor wafer. They are not intended for testing bare singulated die. Thus, the cards cannot be used to test the overall reliability of the bare die to determine whether the die will work for a significant duration of time. Neither do they provide a means for testing the die over a broad range of temperatures.
Other prior art references, such as European patent No. 554,622 issued to Pedder, disclose the use of a test socket in connection with a test station wherein the interface between the bare singulated die and the test socket is a plurality of conductive microbumps soldered onto the test socket contact pads. A problem with such a device is that it is very difficult to manufacture bumps such that pad to bump contact is established for all die bond pads because of the rigidness of the solder microbumps. In other words, use of such bumps introduces planarity problems. Furthermore, the use of such bumps does not insure solid and continuous electrical contact with the bare die bond pads. Additionally, the frequency bandwidth is limited. Thus, these metal bumps do not support all of the types of required tests which may have to be performed even if they do successfully establish electrical continuity with the die bond pads.
Other disclosures utilize a polyimide film upon which metallic microbumps are placed. For example, see Aehr Test, Nitto Denko Develop KGD Solution, Electronics Packaging & Production, September 1993, at 11-12. The article discloses a plurality of gold or nickel plated bumps on polyimide film with a proprietary hole-making technology which connects the bond pads of a die to the pads of a substrate. The use of such a carrier allows for interfacing a bare die to a burn-in board and for conducting burn-in tests. One problem with such an implementation is the difficulty of plating the small microbumps; the disclosure does not adequately disclose the method of plating the microbumps. A second technical problem is the establishing of electrical continuity between the plated bumps and the pads of a substrate or test socket. In fact, in this disclosure, it is clear that this connection means involves the use of a proprietary technology that is not generally available to the public. A third technical problem is damage caused by rigid bumps to die bond pads during temperature excursions typically occurring during high temperature test and burn-in. Finally, this method does not completely solve the previously discussed planarity problem. While the polyimide film establishes some give and take, which helps alleviate the planarity problem, high precision and consistency is still required in order to build a plurality of microbumps, each of which must be sufficiently close to the same plane to establish electrical continuity with the bond pads of the bare die. This occurs because the range of flexible movement resulting from the use of a polyimide film carrying a rigid contact or probe is small. Furthermore, such devices have been known to limit the frequency bandwidth and therefore the types of test and burn-in procedures that can be run or executed.
Other methods of testing bare die include the permanent addition of interface circuitry to the bare die; circuitry which allows the die to be interfaced to a burn-in board. Obvious disadvantages include the increased size and weight of the die packaging. Further, such a solution significantly increases the labor and material costs of testing a bare die. To solve the increased weight and size problem, other disclosures have included the final step of removing or peeling away the added packaging. A well recognized disadvantage of this solution is that the bare die bond pads are frequently damaged as discussed by Falconer and Lippold, A Survey of Techniques for Producing Known Good Die, ISHM-Nordic 31st Annual Conference, at 3 (1993).
Because of the low yield rates of MCMs and because testing singulated bare die has heretofore not been economically feasible or technically acceptable, the costs of MCMs have been high when compared to the creation of circuits comprised of the combination of individual integrated circuits which contain the same die as the MCM. Thus, the MCM manufacturing industry has been suppressed relative to the demand for such a product in part because of the high cost of MCMs. Unless a particular design requires minimization of space and power consumption, the high cost of an MCM is not justified. Therefore, up until now, a need has existed to create an apparatus and method of cost effectively testing bare singulated die to produce "known good die" for inclusion in multi-chip modules.
In addition to there being a need for contacting and testing bare singulated die, there is also a need for contacting and testing other unpackaged fine pitch devices such as semiconductor wafers, individual die in wafer form (wafer probe), packaged semiconductor devices such as micro ball grid arrays and chip-scale packages as well as apparatus for testing or carrying semiconductor devices including bare printed circuit boards, and populated circuit boards.
The basic problem encountered during testing each of the fine pitch devices listed including bare die is related to the ability to contact the contact points given their size and quantity on a typical device. Additionally, the problem continues to become more challenging. Electronic device manufacturing firms continue to push the miniaturization of electronic packaging technologies. For example, low cost quad flat packs are being made continuously thinner and with smaller profile packages. Examples of some of the thinner and smaller packages are the thin quad flat packs ("TQFP") and tape-automated bonding ("TAB") packages. Discrete component packages of capacitors, resistors, and inductors are expected to shrink at least another twenty percent in size. Printed circuit boards and other devices are also continuing to shrink. Some experts believe that the current limit of 0.4 mm pitch in surface mount technology applications will soon be reduced to 0.15 mm pitch.
The trend towards finer pin pitch and package miniaturization is clearly creating new problems and needs in terms of contact and test technology. These current trends will be stymied unless a new technology for contacting the ever increasing number of contact points per square inch and ever decreasing contact point size can be developed successfully so that fine pitch devices may be tested properly at ambient temperature as well as elevated and lowered temperatures, if necessary.
One packaging technique being used to reduce device size is the ball grid array. Ball grid arrays, including ceramic ball grid arrays, are known to deliver far higher densities than packages with leads placed around the perimeter of the package. Another packaging technique that offers even higher densities than ball grid arrays is known as the chip-scale package. Chip-scale packages use leads on a surface that is very slightly larger than the chip within the package.
It is known that all of these new technologies require advancements in substrate technology as well as in burn-in and test techniques. The smallest possible package is no package at all or a bare die. It is known, however, that the use of bare die has been thwarted by their dependence on a viable supply of known good die. More generally, however, the development of all of these types of packaging technologies rely upon development of devices and methods for testing and contacting these increasingly smaller contact points which are continuously increasing in density.
The problem of contacting so many small contact points for these listed devices is the same problem encountered for testing bare die, namely, establishing a solid conductive contact adequate even for burn-in testing in a manner that does not require some sort of bonding to the device being tested.